Exemplary embodiments relate to a method of manufacturing a nonvolatile memory device and, more particularly, to a method of manufacturing a nonvolatile memory device, which is capable of compensating for the concentration of impurity ions in a charge trap layer.
Among nonvolatile memory devices, a NAND flash memory device having a structure advantageous for a high degree of integration is being actively developed. In the NAND flash memory device, a memory cell can be programmed with a desired threshold voltage by controlling electrons trapped/stored in the charge trap layer of the memory cell. The amount of charges trapped into the charge trap layer when the program is performed can be controlled by supplying a specific voltage to a control gate formed over the charge trap layer with a dielectric layer formed therebetween. Accordingly, a coupling ratio, which is a ratio of a voltage supplied to the control gate to a voltage induced to the charge trap layer, becomes an important factor to determine the operating characteristics of the NAND flash memory device. In particular, when the coupling ratio remains consistent, a distribution characteristic with respect to threshold voltages of the device can be prevented from being deteriorated without the occurrence of an Abnormal Program Cell (APC). Further, the failure of a read operation can be prevented as well.
However, the coupling ratio may vary due to a depletion phenomenon occurring in the charge trap layer. The charge trap layer is mainly made of polysilicon including impurity ions. The impurity ions included in the charge trap layer may continue to be discharged externally because of heat generated in subsequent processes. If the concentration of impurity ions included in the charge trap layer is excessively lowered, the depletion phenomenon occurs, which may deteriorate a distribution characteristic of threshold voltages of the device and cause a read operation to fail.
In order to address the above concerns, after forming the charge trap layer including the impurity ions, additional impurity ions may be implanted into the charge trap layer through an additional impurity ion implantation process. However, the additional impurity ions may also be implanted into a portion which is not intended to be implanted (e.g., the active region of a semiconductor substrate used as a channel), and thus the threshold voltage Vt of a memory cell can shift.